1. Field of the Invention
This invention relates generally to methods of fabricating semiconductor devices, and more particularly, to a trim etch process that trims or reduces the critical dimension (CD) of the gate pattern in the resist mask.
2. Discussion of the Related Art
The trend toward ultra large scale integration (ULSI) in semiconductor technology, directed toward an effort to build integrated circuits with more and faster semiconductor devices, has resulted in continued shrinking of critical dimensions of the devices. For example, in circuits having field-effect transistors, a very important process step is the formation of the gate for each of the transistors, and in particular the width of the gate. In many applications, the switching speed and size of the transistor are functions of the width of the transistor gate. A narrower gate tends to produce a higher performance, i.e., faster transistor which is also smaller in size, i.e., narrower in width.
The limitations of conventional lithographic techniques, which are used to pattern the gate during device fabrication, are quickly being realized. Accordingly, there is a continuing need for more efficient and effective fabrication processes for forming transistor gates that are smaller and/or exhibit higher performance.
One technique for achieving narrower gate width is that of trim etch, undertaken on the resist line used to form the gate. Using conventional lithographic techniques, this line may be wider than the desired gate to be formed. For example, a typical deep-UV stepper in certain embodiments provides reliable resolution capabilities down to 0.25 microns. To provide for a gate width that is less than 0.25 microns, the 0.25-micron wide resist line is isotropically etched in a controlled manner in a high-density plasma etching system until a narrower final line remains.
A problem faced with this typical trim etch process is that while it is effective in reducing line width by etching the photoresist in a horizontal direction, a significant amount of the resist is normally etched away in a vertical direction, resulting in substantial weakening and thinning of the photoresist. This significant reduction of the vertical dimension of the photoresist can promote discontinuity thereof, resulting in the photoresist being incapable of providing effective masking m the fabrication of the gate.
Therefore, what is needed is a trim etch process for reducing the critical dimension of a resist line by horizontal etching thereof, meanwhile reducing the etching of the resist line in a vertical direction.
In an embodiment of the present invention, a method is provided for trim etching a line of a resist mask which has an initial width and height. The semiconductor structure incorporating this line of the resist mask is placed in a high-density plasma etching apparatus which utilizes a variety of physical parameters to determine photoresist etch characteristics. One of these parameters, i.e., level of power supplied by a biasing power supply, is reduced to a level lower than has been conventionally used. This results in the ratio of vertical etch rate to horizontal etch rate of the resist being reduced. Thus, reduction of the width of the photoresist line can be achieved, meanwhile with vertical etch of the resist being reduced so as to avoid the problems discussed above.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.